1. Field of the Invention
The present invention relates to an address decoding circuit for a functional block and, more particularly, to an address decoding circuit for a functional block which selects and accesses any memory array divided into, for example, a plurality of blocks.
2. Description of the Prior Art
Conventionally, in accordance with a most common method for producing semiconductor memory, a wafer is cut into chips (small pieces), and each cut chip is sealed into a package. Package containing defective chips due to defects on the wafer are removed, thereby improving a yield.
Meanwhile, with development of a technique for semiconductor, it has been considered to integrate a system function on the wafer (Wafer Scale Integration: WSI). In such WSI, deterioration caused by exposure the package and the outside environment can be prevented, whereby reliability can be improved. In addition, the cost of the package and packaging work can be reduced.
Furthermore, in the WSI, a signal delay caused on the package or on a packaging board can be reduced. More specifically, in the method of packaging the wafer, the following steps are required, i.e, wiring between each chip and terminals of the package when the chips cut from the wafer are sealed in packages; arranging those packages on the printed circuit board; and connecting between terminals of each package in accordance with a pattern, whereby signal delay caused by the wiring and the pattern would result. In contrast, in the WSI, since chips are directly wired, the signal delay can be reduced. In addition, the WSI has an advantage that packaging density can be improved.
FIG. 1 is a diagram showing a structure of the conventional WSI. FIG. 1 shows an example of a memory LSI and a plurality of memory arrays Uf's divided into blocks are arranged on a wafer 1. In addition, in the case where memory arrays Uf's include some defects, spare memory arrays Us's to be replaced with those are also arranged. A control signal system, an address signal line and a data input/output line are provided between these pluralities of memory cell arrays Uf's and spare memory arrays Us's, where a branch selecting circuit BS selects any memory in the memory array blocks by an address signal and a branch selecting signal and data is inputted and outputted by a data buffer circuit DB.
If a defective memory block is included in the memory arrays Uf's, it is electrically replaced with a spare memory array Us. Therefore, the desired number of operative blocks can be obtained in the whole wafer. As a result, the address signal and data input/output of the block can be switched by an electrically programmable device (electric fuse).
With a high degree of integration of a MOS RAM of large capacity, the rate of data input/output has been improved conventionally. Each block of the above described WSI conventionally may be driven in either of the following two methods.
(1) The rate of data input/output is increased by implementing the MOS RAM in multibit structure. However, in that case, because 8 bits or 16 bits of data is collectively inputted and outputted in parallel, the area of a parallel operating portion inside the chip is increased and the number of terminals of a package is increased, whereby the degree of integration is disadvantageously diminished at both chip level and packaging level. PA1 (2) Many bits are serially inputted and outputted at high speed with a shift register provided on a data input/output portion. In that case, the above described disadvantage explained in (1) does not occur. However increase in chip area in required for arrangement of the shift register. PA1 (3) The number of terminals of a package are further reduced by serially inputting control signals from one terminal by serially performing address input and data input/output using one terminal. PA1 .circle.1 Row address set: A cycle for inputting a row address in which the succeeding cycle is performed. PA1 .circle.2 Reading/refresh: A cycle for detecting and amplifying memory cell data by a sense amplifier. PA1 .circle.3 Writing: A cycle for writing data from a shift register to a sense amplifier system. PA1 .circle.4 Serial input: A cycle for setting external input data into a shift register. PA1 .circle.5 Serial output: A cycle for outputting serial data from a shift register. PA1 .circle.1 When a memory cell array of a serial input of a row address is 1M bit and the number of word lines is 1024 (=2.sup.10), the number of bits of the shift register needs 10 bits. PA1 .circle.2 and .circle.3 : and As the reading/refresh and writing are of only one cycle, these have nothing to do with the data input. PA1 .circle.4 A cycle for serially setting the data input into the shift register. The number of bits as much as the required number is needed. For example, when the memory cell array is 1M bit and the number of sense amplifiers is 1024 (=2.sup.10), it needs 1024 cycles. PA1 .circle.5 : A serial data output is performed in order from the first bit. When data for one row is read, it needs 1024 cycles as in the case of .circle.4 .
As a method which further improves the above described advantage in (2), the following method has been proposed.
By a combination of the above described methods (2) and (3), a packaging density is remarkably improved and data can be inputted and outputted at high speed. As an example of such a structure, FIG. 2 shows a dynamic MOSRAM.
Referring to FIG. 2, four terminals i.e. an external terminal V.sub.cc (power supply), V.sub.ss (ground), a clock input terminal and a data input/output terminal are provided. A dynamic MOSRAM 2 comprises a memory cell array 21, a row decoder 22, a sense amplifier 23, a shift register 24, a serial/parallel converting circuit 25, a row address buffer 26, a control signal generating circuit 27, a data in buffer 28 and a data out buffer 29.
The memory cell array 21 comprises, though not shown, a plurality of word lines, a plurality of bit line pairs crossing the word lines at right angles and memory cells arranged on the intersections of both. The row decoder 22 selects the corresponding word line in response to a row address signal externally inputted to the row address buffer 26 through the data input terminal and the serial/parallel converting circuit 25. When any word line is selected, data stored in memory cells for one selected row appears as a signal potential on the bit line pair. This signal potential is detected and amplified by the sense amplifier 23.
Each memory cell is a one-transistor one-capacitor type and the sense amplifier 23 also operates to refresh data of each memory cell. In addition, the sense amplifier 23 serves as a data latch and it is connected to the shift register 24 for every bit line. The shift register 24 is connected to the data in buffer 28 and data out buffer 29. Data serially inputted to the data input terminal is converted in parallel by the serial/parallel converting circuit 25 and the converted data is applied to the shift register 24 through the data in buffer 28. When data is read, data detected and amplified by the sense amplifier 23 is applied to the shift register 24 and serially selected in accordance with shift operation of the shift register 24 and outputted to the data out buffer 29.
When data is written, data to be written sent from the data in buffer 28 is serially shifted by the shift register 24 and written from the bit line pair to the corresponding memory cell through the corresponding sense amplifier 23. The serial/parallel converting circuit 25 operates to make a serial/parallel conversion in accordance with a clock signal applied to the clock signal input terminal, for outputting data inputted from the data input terminal to the data in buffer 28, row address buffer 26 and control signal generating circuit 27.
FIG. 3A is a timing diagram for explaining operation of the dynamic MOSRAM shown in FIG. 2. FIG. 3 shows an operational timing for a certain cycle, where one cycle is a time period from reset operation to reset operation. When the clock input rises, the data input is at the "L" level. As a result, the memory cell array 21, the shift register 24 and the serial/parallel converting circuit 25 are reset (initialized).
After the reset operation, if the data input becomes "H" level when the clock rises, a certain cycle is started and when the clock falls, a control input, a row address input and a data input are performed and also a data output is started. More specifically, first three-bit input of each cycle C.sub.0, C.sub.1, C.sub.2) are the control inputs thereby specifying basic operation of the cycle. The basic operation comprises .circle.1 to .circle.5 shown in FIG. 3B.
Any one of the above mentioned operations .circle.1 to .circle.5 is selected in accordance with a combination of data C.sub.0, C.sub.1 and C.sub.2. The succeeding data inputs from the fourth bit are as follows in accordance with each cycle.
Memory operation is actually performed by a combination of the above mentioned five kinds of cycles .circle.1 to .circle.5 .
When the above mentioned driving method is employed in each block of the WSI, it is necessary to input a block address signal in the same manner as the above description and select a block thereby. More specifically, block selection is performed by serially inputting the block address signal to each block in the same manner as that of the above mentioned row address input cycle and serial/parallel converting the same at each block to determine whether it is a block address corresponding to the block or not.
In such a case, a serial/parallel converting system of the block address and a block address decoder are needed at every block. In addition, it is necessary to construct the block address decoder so as to be programmed by a programmable device at every block when it is manufactured because each of the blocks has different circuits. Therefore a circuit structure becomes complicated and area thereof is increased.
FIG. 4 is a diagram showing another example of a conventional block selection. In the example shown in FIG. 4, a plurality of blocks 31 . . . 3n and 41 . . . 4n are serially interconnected by one address line. A buffer is comprised in each of the blocks 31 . . . 3n and 41 .. . 4n, and address line fuses 51 . . . 5n and 61 . . . 6n are connected to the address line corresponding to respective buffers. Therefore, an address signal is serially transferred to each of blocks 31 . .. 3n and 41 . . . 4n through the address line.
In testing, a good block operating normally is distinguished from a defective block not operating normally, an address line fuse corresponding to the good block is cut and an address line fuse corresponding to the defective block is not cut off, whereby a short-circuit is made between input and output of the buffer so that a bypass is made with the result that the address signal is not inputted into the defective block by the address line fuse. Consequently, the address signal is inputted into only good blocks and only good blocks are serially connected in order. As for the defective blocks, since the address signal is bypassed by the corresponding address line fuse, the address signal is not inputted into the defective blocks
The address signal in each block is processed on the bases of 1 bit shift register and if the number of good blocks is n in all, n-bit shift register connected by the address line is provided. In the 1-bit shift register in each block, when the level becomes "H" level, its block becomes "selection" state. A 1-bit "H" level signal is applied as part of the address signal to an address input. Thereafter, the address signal operates the 1-bit shift register in a normal block, while it is transferred from block to block and when the address signal is transferred to a desired block (if the desired block is the i-th block, shift operation is performed i times), the block becomes a selected state. In this method, if the total number of blocks is n, the shift operation needs to be repeated n times. Therefore, the larger the number of blocks, the longer it takes for shift operation.